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P12C3DYYR 데이터시트(PDF) 17 Page - Texas Instruments |
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P12C3DYYR 데이터시트(HTML) 17 Page - Texas Instruments |
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17 / 30 page ![]() 9.4.2 Layout Example Figure 9-9. Typical Layout Keep the VDD capacitor close to the VDD pin Route sense traces S1, S2, S3 and S4 away from the INJ trace Keep the damping network close to the INJ pin Place the compensation network close to the COMP1 and COMP2 pins INJ pin probe point Top layer copper Legend Layer-2 GND plane Top solder Figure 9-10. Typical Top-Layer Design www.ti.com TPSF12C3 SNVSCB8 – MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSF12C3 |
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