82P33731 datasheet(21/66 Pages) RENESAS

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August 28, 2017

82P33731 Datasheet

manually set to go into holdover, the initial frequency accuracy is

4.4X10-8 ppm.

DPLL2_auto_avg = 1: averaged frequency value is used as holdover

frequency. The holdover average bandwidth is about 1.5mHz. In this

mode the initial frequency offset is 1.1e-5ppm assuming that there is no

in-band jitter/wander at the input just before entering holdover state.

3.2.2.2.4 Frequency Offset Limit

The DPLL2 output is limited to be within the DPLL hard limit (refer to

Chapter 3.2.4.3).

3.2.3

INPUT CLOCKS AND FRAME SYNC

The 82P33731 has 14 input clocks that can also be used for frame

sync pulses.

The 82P33731 supports Telecom and Ethernet frequencies from

1PPS up to 650 MHz.

IN1 and IN2 support the AMI input signal only. The input clock is a 64

kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock. The 400hz_-

sel bit should be set to match the input frequency. Any input violation

that does not meet the standard composite clock structure will trigger an

AMI violation. The AMI violation is indicated by the AMI1_VIOL/

AMI2_VIOLbit, which will trigger an interrupt on INT_REQ pin if there is

an AMI violation and the respective interrupt mask bit is set. By default

the interrupt mask bit is not set.

Any of the input clocks can be used as a frame pulse or sync signal.

The SYNC_sel[3:0] bits in INn_los_sync_cnfg (14 < n < 1) registers sets

which pin is used as frame pulse or sync signal.

IN3 to IN14 can be used for 2 kHz, 4 kHz or 8 kHz frame pulses or

1PPS sync signal.The input frequency should match the setting in the

sync_freq[1:0] bits in DPLL1_input_mode_cnfg register.

3.2.3.1

Input Clock Pre-divider

Each input clock is assigned an internal Pre-divider. The Pre-divider

can be used to divide the clock frequency down to a convenient fre-

quency, such as 8 kHz for the internal DPLL1. Note that T1 and E1 refer-

ences can exhibit substantial jitter with frequencies above 4 kHz. These

references should be applied to DPLL1 without being divided down to 8

kHz.

For IN1 and IN2, the DPLL required frequency is fixed to 8 kHz (i.e.,

the corresponding IN_FREQ[3:0] bits are ‘0000’). The 8 kHz clock is

extracted from the composite clock and the Pre-divider is bypassed

automatically.

For IN3 ~ IN14, the DPLL required frequency is set by the corre-

sponding IN_FREQ[3:0] bits.

Table 8: IN_FREQ[3:0] DPLL Frequency

IN_FREQ[3:0] Bits

DPLL Frequency

0000

8 kHz

0001

1.544 MHz / 2.048 MHz (depends on SONET/ SDH bit)

0010

6.48 MHz

0011–1000

Reserved

1001

2 kHz

1010

4 kHz

1011

1 PPS

1100

6.25 MHz

1101–1111

Reserved

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