PCI Express™ Jitter Attenuator

874005 DATA SHEET

2

REVISION B 7/20/15

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3A. OUTPUT ENABLE FUNCTION TABLE

TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL

Inputs

Outputs

OEA/OEB

QAx/nQAx

QBx/nQBx

0

HiZ

HiZ

1

Enabled

Enabled

Number

Name

Type

Description

1, 24

nQB2, QB2

Output

Differential output pair. LVDS interface levels.

2, 3

nQA1, QA1

Output

Differential output pair. LVDS interface levels.

4, 23

V

DDO

Power

Output supply pins.

5, 6

QA0, nQA0

Output

Differential output pair. LVDS interface levels.

7

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs (nQx) to go low and the inverted outputs

(Qx) to go high. When logic LOW, the internal dividers and the outputs

are enabled. LVCMOS/LVTTL interface levels.

8

BW_SEL

Input

Pullup/

Pulldown

PLL Bandwidth input. See Table 3B.

9V

DDA

Power

Analog supply pin.

10

F_SELA

Input

Pulldown

Frequency select pin for QAx,nQAx outputs.

LVCMOS/LVTTL interface levels.

11

V

DD

Power

Core supply pin.

12

OEA

Input

Pullup

Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are

active. When LOW, the QAx,nQAx outputs are in a high impedance state.

LVCMOS/LVTTL interface levels.

13

CLK

Input

Pulldown Non-inverting differential clock input.

14

nCLK

Input

Pullup

Inverting differential clock input.

15, 16

GND

Power

Power supply ground.

17

OEB

Input

Pullup

Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are

active. When LOW, the QBx,nQBx outputs are in a high impedance state.

LVCMOS/LVTTL interface levels.

18

F_SELB

Input

Pulldown

Frequency select pin for QBx,nQBx outputs.

LVCMOS/LVTTL interface levels.

19, 20

nQB0, QB0

Output

Differential output pair. LVDS interface levels.

21, 22

nQB1, QB1

Output

Differential output pair. LVDS interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

Inputs

PLL Band-

width

PLL_BW

0

~200kHz

1

~800kHz

Float

~400kHz