STM32H7B0IB datasheet(195/205 Pages) STMICROELECTRONICS

195 / 205 page

Date

Revision

Changes

Section 6.3.19 Octo-SPI interface characteristics:

•

Updated tS(IN)//tH(IN) conditions and minimum values in Table 88. OCTOSPI

characteristics in SDR mode and updated Figure 40. OctoSPI timing

diagram - SDR mode.

•

Updated Table 89. OCTOSPI characteristics in DTR mode (with DQS)/

Octal and Hyperbus and Figure 41. OctoSPI timing diagram - DTR mode.

•

Updated Figure 42. OctoSPI Hyperbus clock, Figure 43. OctoSPI Hyperbus

read and Figure 44. OctoSPI Hyperbus write.

Table 116. SPI dynamic characteristics:

•

Changed tsu(MI) and th(MI) minimum values in Master mode.

•

Removed tw(SCKH), tw(SCKL).

Table 120. Dynamics characteristics: SDMMC characteristics, VDD=2.7 to 3.6 V:

•

Modified tISU and tIH minimum values for CMD/ D inputs in High-speed

mode.

•

Modified tISUD and tIH minimum values for CMD/ D inputs in Default mode.

Table 121. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V:

•

Removed SDIO_CK/fPCLK2 frequency ratio.

•

Modified tISU and tIH minimum values in CMD, D inputs (referenced to CK)

in eMMC mode.

Section 7.5 UFBGA169 package information:

•

Added note 2 below Figure 85. UFBGA169 - Outline.

•

Updated Table 130. UFBGA169 - Mechanical data.

•

Removed note related to non-solder mask below Figure 86. UFBGA169 -

Recommended footprint.

Section 7.6 UFBGA(176+25) package information:

•

Added note 2 below .

•

Updated .

19-May-2022

Renamed SPIx_NSS signal into SPIx_SS.

Updated Table 18. Current characteristics.

Removed fTraceCK / fJTCK from Table 21. Maximum allowed clock frequencies.

Updated note 3 in Table 38. Typical current consumption in System Stop mode.

Updated Table 64. Output voltage characteristics for all I/Os except PC13, PC14,

PC15 and PI8 and Table 65. Output voltage characteristics for PC13, PC14,

PC15 and PI8. Added Table 68. Pxy_C and Pxy analog switch characteristics.

Added note to td(SDCLKL- SDNE) maximum value in Table 84. SDRAM read

timings, Table 85. LPSDR SDRAM read timings, Table 86. SDRAM write timings

and Table 87. LPSDR SDRAM write timings.

Updated Figure 47. Typical connection diagram using the ADC with FT/TT pins

featuring analog switch function and notes below figures.

Added note to tSAMP in Table 94. DAC characteristics.

Updated Table 106. DFSDM measured timing 1.62-3.6 V.

In Table 115. USART characteristics, replaced tsu(SI) and tsu(MI) by tsu(RX), th(SI)

and th(MI) by th(RX), tv(SO) and tv(MO) by tv(TX), and th(SO) and th(MO) by th(TX).

Updated Section 7.1 LQFP64 package information, Section 7.2 LQFP100

package information, Section 7.5 UFBGA169 package information and

Section 7.6 UFBGA(176+25) package information.

Added Section Important security notice.

STM32H7B0xB

DS13196 - Rev 7

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