STM32H7B3II datasheet(113/238 Pages) STMICROELECTRONICS

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Symbol

Parameter

Conditions

Min(1) Typ(1) Max(1) Unit

Jitter

Cycle-to-cycle jitter

fVCO_OUT = 560 MHz

±ps

Long term jitter

Normal mode (f PLL_IN = 2 MHz), fVCO_OUT = 560 MHz

±0.2

Normal mode (f PLL_IN = 16 MHz), fVCO_OUT = 560 MHz

±0.8

Sigma-delta mode (f PLL_IN = 2 MHz), fVCO_OUT = 560 MHz

±0.2

Sigma-delta mode (f PLL_IN = 16 MHz), fVCO_OUT = 560 MHz

±0.8

IDD(PLL)

PLL power consumption

fVCO_OUT = 560 MHz

VDD

330

420

µA

VCORE

630

fVCO_OUT = 128 MHz

VDD

155

230

VCORE

170

1. Guaranteed by design, unless otherwise specified.

2. This value must be limited to the maximum frequency due to the product limitation.

3. Guaranteed by characterization results.

Table 56. PLL characteristics (medium VCO frequency range)

Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)

Unit

fPLL_IN

PLL input clock

MHz

PLL input clock duty cycle

fPLL_OUT

PLL multiplier output clock P, Q, R

VOS0

1.17

210

MHz

VOS1

1.17

210

VOS2

1.17

160(2)

VOS3

1.17

88(2)

fVCO_OUT PLL VCO output

150

420

tLOCK

PLL lock time

Normal mode

80(3)

µs

Sigma-delta mode

forbidden

Jitter

Cycle-to-cycle jitter

fVCO_OUT = 150 MHz

±ps

fVCO_OUT = 200 MHz

fVCO_OUT = 400 MHz

fVCO_OUT = 420 MHz

Period jitter

fVCO_OUT = 150 MHz

fPLL_OUT = 50 MHz

±-ps

fVCO_OUT = 400 MHz

Long term jitter

Normal mode, fVCO_OUT = 400 MHz

±0.2

IDD(PLL)

PLL power consumption on VDD

fVCO_OUT = 420 MHz

VDD

275

360

µA

VCORE

450

fVCO_OUT = 150 MHz

VDD

160

240

VCORE

165

1. Guaranteed by design, unless otherwise specified.

2. This value must be limited to the maximum frequency due to the product limitation.

3. Guaranteed by characterization results.

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 113/238

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