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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32U535NET6QTR 데이터시트(PDF) 218 Page - STMicroelectronics |
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STM32U535NET6QTR 데이터시트(HTML) 218 Page - STMicroelectronics |
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218 / 278 page  Electrical characteristics STM32U535xx 218/278 DS14217 Rev 1 5.3.19 12-bit analog-to-digital converter (ADC4) characteristics Unless otherwise specified, the parameters given in the table below are values derived from tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage conditions summarized in Table 32. Note: It is recommended to perform a calibration after each power-up. Table 104. 12-bit ADC4 characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog power supply for ADC ON -1.62 - 3.6 V VREF+ Positive reference voltage - 1 - VDDA VREF- Negative reference voltage - VSSA fADC ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 0.14 - 55 MHz ADC clock duty cycle - 45 - 55 % fs Sampling rate Resolution = 12 bits 0.01 - 2.75 Msps Resolution = 10 bits 0.012 - 3.05 Resolution = 8 bits 0.014 - 3.43 Resolution = 6 bits 0.0175 - 3.92 tTRIG External trigger period Resolution = 12 bits 16 - - 1/fADC VAIN(3) Conversion voltage range - 0 - VREF+ V RAIN(4) External input impedance Tj = 130 °C Resolution = 12 bits - - 2.2 kΩ Resolution = 10 bits - - 6.8 Resolution = 8 bits - - 33.0 Resolution = 6 bits - - 47.0 CADC Internal sample and hold capacitor -- 5 - pF tADCVREG_ STUP ADC LDO startup ready flag time - - - 25 µs tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle tOFF_CAL Offset calibration time - 82 1/fADC tLATR Trigger conversion latency WAIT = 0, AUTOFF = 0, DPD = 0, fADC = HCLK 4 WAIT = 0, AUTOFF = 0, DPD = 0, fADC = HCLK/2 4 WAIT = 0, AUTOFF = 0, DPD = 0, fADC = HCLK/4 3.75 ts Sampling time - 1.5 - 814.5 |
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