STM32U535NET6QTR datasheet(226/278 Pages) STMICROELECTRONICS

226 / 278 page

Electrical characteristics

STM32U535xx

226/278

DS14217 Rev 1

Figure 39. 12-bit buffered/non-buffered DAC

IDDV(DAC)

DAC consumption

from VREF+

DAC output

buffer ON

No load, middle

code (0x800)

170

240

µA

No load, worst

code (0x0E4)

300

400

DAC output

buffer OFF

No load,

middle/worst code

(0x800)

145

180

Sample and hold mode, buffer

ON, CSH = 100 nF (worst code)

170 × TON

/(TON +

TOFF)

(4)

400 × TON

/(TON +

TOFF)

(4)

Sample and hold mode, buffer

OFF, CSH = 100 nF (worst code)

145 × TON

/(TON +

TOFF)

(4)

180 × TON

/(TON +

TOFF)

(4)

1. Specified by design. Not tested in production.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

3. Refer to Table 91: I/O static characteristics.

4. TON is the refresh phase duration. TOFF is the hold phase duration (see the product reference manual for more details).

Table 111. DAC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv47959V2

12-bit

digital-to-analog

converter

Buffered/non-buffered DAC

DAC_OUTx

RLOAD

CLOAD

Buffer

(1)

(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads

directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in

the DAC_CR register.

Table 112. DAC accuracy(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DNL

Differential

non-linearity(2)

DAC output buffer ON

±2

LSB

DAC output buffer OFF

±2

Monotonicity

10 bits

guaranteed

INL

Integral

non-linearity(3)

DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ

±4

LSB

DAC output buffer OFF, CL ≤ 50 pF, no RL

±4

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