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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM8AF6346ITD 데이터시트(PDF) 53 Page - STMicroelectronics |
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STM8AF6346ITD 데이터시트(HTML) 53 Page - STMicroelectronics |
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53 / 95 page  DS12343 Rev 2 53/95 STM8AF6366 Electrical characteristics 93 Table 22. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2(1) 1. Guaranteed by design. - ∞ µs/V VDD fall time rate - 2(1) - ∞ tTEMP Reset release delay VDD rising - 1 1.7 ms Reset generation delay VDD falling - 3 - µs VIT+ Power-on reset threshold(2) (3) 2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is kept. The EEPROM programming sequence must not be initiated. 3. There is inrush current into VDD present after device power on to charge CEXT capacitor. This inrush energy depends from CEXT capacitor value. For example, a CEXT of 1μF requires Q=1 μF x 1.8V = 1.8 μC. - 2.65 2.8 2.95 V VIT- Brown-out reset threshold - 2.58 2.73 2.88 VHYS(BOR) Brown-out reset hysteresis -- 70(1) -mV |
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