| 전자부품 데이터시트 검색엔진 |
|
STEF12E 데이터시트(PDF) 18 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STEF12E 데이터시트(HTML) 18 Page - STMicroelectronics |
|
18 / 19 page ![]() List of figures Figure 1. Block diagram .................................................................... 2 Figure 2. Pin configuration (top view) ........................................................... 3 Figure 3. Application circuit .................................................................. 6 Figure 4. Typical HDD application circuit ......................................................... 6 Figure 5. Delay time and VOUT ramp-up time ...................................................... 8 Figure 6. En/fault pin status .................................................................. 8 Figure 7. Clamping voltage vs. temperature ....................................................... 9 Figure 8. UVLO voltage vs. temperature ......................................................... 9 Figure 9. UVLO hysteresis vs. temperature ....................................................... 9 Figure 10. Off-state voltage vs. temperature ....................................................... 9 Figure 11. Bias current (device operational)........................................................ 9 Figure 12. ON-resistance vs. temperature ......................................................... 9 Figure 13. Current limit vs. RLimit .............................................................. 10 Figure 14. Thermal latch delay vs. power ........................................................ 10 Figure 15. VOUT ramp-up vs. enable ............................................................ 10 Figure 16. VOUT clamping ................................................................... 10 Figure 17. Line transient .................................................................... 10 Figure 18. Startup into output short-circuit ........................................................ 10 Figure 19. Thermal latch from 2 A load to short-circuit................................................ 11 Figure 20. Startup into output short-circuit (fast rise) ................................................. 11 Figure 21. DFN10 (3x3 mm) package outline ...................................................... 12 Figure 22. DFN10 (3x3 mm) recommended footprint................................................. 13 Figure 23. DFN10 (3x3 mm) tape and reel outline................................................... 14 STEF12E List of figures DS12800 - Rev 2 page 18/19 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |