7.3

Interfacing the ADC1283

The conversion starts on a falling edge of CS and stops on a rising edge of CS. An internal 8-bit register contains

the address of the channel to be converted. 3 bits of this register are used to this purpose.

By default, if no value is written inside the register or if a wrong address is entered, channel 0 (IN0) is converted

and outputted on DOUT after the first conversion cycle. This address register is reset to its default value (IN0)

when (CS) goes high.

At the start of the conversion, the first data present on DOUT after 16 clock cycles is always channel 0 (IN0). To

get the information on another channel after starting conversion, 32 clock cycles are necessary (equivalent to two

12-bit words).

THE ADC1283 enters track mode under three different conditions. When (CS) goes low with SCLK high, the ADC

enters track mode on the first falling edge of SCLK. When (CS) goes low with SCLK low, the ADC automatically

enters track mode and the falling edge of (CS) is seen as the first falling edge of SCLK. Finally, when (CS) and

SCLK go low simultaneously, the ADC enters track mode. While there is no timing restriction with respect to the

rising edges of (CS) and SCLK, see Figure 5 for set-up and hold time requirements for the falling edge of (CS)

with respect to the rising edge of SCLK.

3 clock cycles are necessary to charge the capacitance to memorize the level of the signal. The signal is then

evaluated during 13 clock cycles. DOUT is always on the same format: four digital 0’s followed by 12-bit signal

(MSB first).

Conversion stops on (CS) turning high but if (CS) remains low, the ADC1283 continuously converts the analog

signal on the selected channel.

For further information, please look at the Application Note related to the ADC1283.

ADC1283

Interfacing the ADC1283

DS13932 - Rev 1

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