FN3325 Rev 0.00

Page 1 of 9

December 1992

FN3325

Rev 0.00

December 1992

CD4076BMS

CMOS 4 -Bit D-Type Registers

DATASHEET

Pinout

CD4076BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

M

N

Q1

Q2

Q3

Q4

VSS

CLOCK

VDD

DATA 1

DATA 2

DATA 3

DATA 4

G2

G1

RESET

DATA

INPUT

DISABLE

OUTPUT

DISABLE

4D - TYPE

FLIP-FLOPS

WITH

AND-OR

LOGIC

CLOCK

RESET

7

15

G1

G2

M

N

910

1

2

D1

D2

D3

D4

14

13

12

11

Q1

Q2

Q3

Q4

3

4

5

6

VSS = 8

VDD = 16

DATA INPUT

DISABLE

OUTPUT

DISABLE

Features

• High Voltage Type (20V Rating)

• Three State Outputs

• Input Disabled Without Gating the Clock

• Gated Output Control Lines for Enabling or Disabling

the Outputs

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

A at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Description

CD4076BMS types are four-bit registers consisting of D-type

flip-flops that feature three-state outputs. Data Disable inputs

are provided to control the entry of data into the flip-flops.

When both Data Disable inputs are low, data at the D inputs

are loaded into their respective flip-flops on the next positive

transition of the clock input. Output Disable inputs are also

provided. When the Output Disable inputs are both low, the

normal logic states of the four outputs are available to the

load. The outputs are disabled independently of the clock by

a high logic level at either Output Disable input, and present

a high impedance.

The CD4076BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

H4T

Frit Seal DIP

H1E

Ceramic Flatpack

H6W