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CD4512BMS 데이터시트(PDF) 8 Page - Renesas Technology Corp |
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CD4512BMS 데이터시트(HTML) 8 Page - Renesas Technology Corp |
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8 / 8 page ![]() CD4512BMS FN3340 Rev 0.00 Page 8 of 8 December 1992 Chip Dimensions and Pad Layouts Dimensions in parentheses are in milimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch.) METALLIZATION: Thickness: 11k Å 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6k Å, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (“A” SELECT TO OUTPUT) Typical Performance Characteristics (Continued) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 10V 5V LOAD CAPACITANCE (CL) (pF) 040 60 80 100 20 0 50 100 150 200 250 300 75 70 60 50 40 30 20 10 0 0 102030 40 50 60 70 78 72-80 (1.829-2.032) 75-83 (1.905-2.108) 4-10 (0.102-0.254) |
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