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March 31, 2008

IDT80KSW0004

Datasheet

Reads during Configuration Register Access

Reads are much like writes except that target data is not provided. When bit 0 of the data stream is 1, data shifted out will be read from the address

specified in jtag_config_addr. TDI will not be used after the address is shifted in. As a function of read latency in the architecture, the first 16 bits will

be 0’s and must be ignored. The following bits will contain the actual register bits.

Figure 26 Implementation of read during configuration register access

JTAG DC Electrical Specifications

At recommended operating conditions with VDD3 = 3.3V ± 5%

Table 31 JTAG DC Electrical Specifications (VDD3 = 3.3V ± 5%)

Shift_dr

Capture_dr

Shift_dr

Pause_dr

Exit1_dr

Exit2_dr

Update_dr

Exit1_dr

Exit2_dr

Pause_dr

Select_dr_scan

TAP controller

state

TDI

Address

TDO

Z

ZZ

Data

Read latency

Data 1

Internal

address

Address

Internal

data

Data

Parameter

Symbol

Min

Max

Unit

3.3V Supply Voltage

VDD3

3.15

3.45

V

Ground

VSS

0

0

V

Input high voltage level

VIH

2.0

VDD3(max) + 0.15

V

Input low voltage level

VIL

-0.3

0.8

V

Output Low Voltage (IOL = 4mA, VDD3 = Min.)

VOL

-

0.4

V

Output High Voltage (IOH = -4mA, VDD3 =

Min.)

VOH

2.4

-

V

Input current for JTAG pins (input voltage is

between 0.1 x VDD3 and 0.9 x VDD3 (max))

ILI

-30

30

uA

Capacitance for each Input pin

CIN

-

8

pF

Capacitance for each I/O or Output pin

COUT

-

10

pF