Data Sheet

ADPA1122

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 17

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3, 12, 13

VDD3A, VDD2A, VDD1, VDD2B, VDD3B

Power Supply Voltage for the Power Amplifier. First, second, and third stage drain bias. See Figure 3 for

the interface schematic.

4

VGG1

Gate Bias Voltage. See Figure 4 for the interface schematic.

5, 9, 11, 14

NIC

Not Internally Connected. The NIC pins are not connected internally. However, all data shown was

measured with the NIC pins connected to RF and dc ground externally.

6, 8, 15, 17

GND

Ground. The GND pins must be connected to RF and dc ground. See Figure 5 for the interface

schematic.

7

RFIN

RF Input. The RFIN pin is ac-coupled in the signal path and is matched to 50 Ω. See Figure 6 for the

interface schematic. If the RFIN pin is externally connected to a DC bias level other than 0 V, ac-couple

the RFIN pin externally because of the internal DC path to ground.

10

VREF

Reference Diode for Temperature Compensation of VDET RF POUT Measurements. See Figure 8 for the

interface schematic.

16

RFOUT

RF Output. The RFOUT pin is ac-coupled and is matched to 50 Ω. See Figure 7 for the interface

schematic.

18

VDET

Detector Diode to Measure RF POUT. POUT detection via the VDET pin requires the application of a DC

bias voltage through an external series resistor. Used in combination with the VREF pin, the difference

voltage (VREF voltage (VREF) − VDET voltage (VDET)) is a temperature compensated DC voltage that is

proportional to the RF POUT. See Figure 9 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to RF and dc ground.