P87LPC762FN datasheet(19/57 Pages) PHILIPS

19 / 57 page

Philips Semiconductors

Preliminary data

87LPC762

Low power, low price, low pin count (20 pin)

microcontroller with 2 kbyte OTP

2001 Oct 26

Table 1. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER

SLAVEN,

MASTRQ,

MASTER

TIRUN

OPERATING MODE

All 0

The I2C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I2C

application wants to ignore the I2C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.

All 0

The I2C interface is disabled.

Any or all 1

The I2C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do

not, so that there is no checking for I2C being “hung.” This configuration can be used for very slow I2C operation.

Any or all 1

The I2C interface is enabled. Timer I runs during frames on the I2C, and is cleared by transitions on SCL, and by

Start and Stop conditions. This is the normal state for I2C operation.

Table 2. CT1, CT0 Values

CT1, CT0

Min Time Count

(Machine Cycles)

CPU Clock Max

(for 100 kHz I2C)

Timeout Period

(Machine Cycles)

1 0

8.4 MHz

1023

0 1

7.2 MHz

1022

0 0

6.0 MHz

1021

1 1

4.8 MHz

1020

Interrupts

The 87LPC762 uses a four priority level interrupt structure. This

allows great flexibility in controlling the handling of the 87LPC762’s many

interrupt sources. The 87LPC762 supports up to 12 interrupt sources.

Each interrupt source can be individually enabled or disabled by

setting or clearing a bit in registers IEN0 or IEN1. The IEN0

interrupts at once.

Each interrupt source can be individually programmed to one of four

priority levels by setting or clearing bits in the IP0, IP0H, IP1, and

IP1H registers. An interrupt service routine in progress can be

interrupted by a higher priority interrupt, but not by another interrupt

of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. So, if two

requests of different priority levels are received simultaneously, the

request of higher priority level is serviced.

If requests of the same priority level are received simultaneously, an

internal polling sequence determines which request is serviced. This

is called the arbitration ranking. Note that the arbitration ranking is

only used to resolve simultaneous requests of the same priority level.

Table 3 summarizes the interrupt sources, flag bits, vector

addresses, enable bits, priority bits, arbitration ranking, and whether

each interrupt may wake up the CPU from Power Down mode.

Table 3. Summary of Interrupts

Description

Interrupt

Flag Bit(s)

Vector

Address

Interrupt

Enable Bit(s)

Interrupt

Priority

Arbitration

Ranking

Power Down

Wakeup

External Interrupt 0

IE0

0003h

EX0 (IEN0.0)

IP0H.0, IP0.0

1 (highest)

Yes

Timer 0 Interrupt

TF0

000Bh

ET0 (IEN0.1)

IP0H.1, IP0.1

External Interrupt 1

IE1

0013h

EX1 (IEN0.2)

IP0H.2, IP0.2

Yes

Timer 1 Interrupt

TF1

001Bh

ET1 (IEN0.3)

IP0H.3, IP0.3

Serial Port Tx and Rx

TI & RI

0023h

ES (IEN0.4)

IP0H.4, IP0.4

Brownout Detect

BOD

002Bh

EBO (IEN0.5)

IP0H.5, IP0.5

Yes

I2C Interrupt

ATN

0033h

EI2 (IEN1.0)

IP1H.0, IP1.0

KBI Interrupt

KBF

003Bh

EKB (IEN1.1)

IP1H.1, IP1.1

Yes

Comparator 2 interrupt

CMF2

0043h

EC2 (IEN1.2)

IP1H.2, IP1.2

Yes

Watchdog Timer

WDOVF

0053h

EWD (IEN0.6)

IP0H.6, IP0.6

Yes

Comparator 1 interrupt

CMF1

0063h

EC1 (IEN1.5)

IP1H.5, IP1.5

Yes

Timer I interrupt

–

0073h

ETI (IEN1.7)

IP1H.7, IP1.7

12 (lowest)

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