January 22, 2020

12

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

87016I DATASHEET

Differential Clock Input Interface

The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both signals must meet the VPP and VCMR

input requirements. Figures 2A to 2E show interface examples for the

CLK/CLK input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the

vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 2A, the input termination

applies for Renesas LVHSTL drivers. If you are using an LVHSTL

driver from another vendor, use their termination recommendation.

Figure 2A. CLK/CLK Input Driven by a Renesas

LVHSTL Driver

Figure 2C. CLK/CLK Input Driven by a

3.3V LVPECL Driver

Figure 2E. CLK/CLK Input Driven by a

3.3V LVPECL Driver with AC Couple

Figure 2B. CLK/CLK Input Driven by a

3.3V LVPECL Driver

Figure 2D. CLK/CLK Input Driven by a 3.3V LVDS Driver

R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input