P87LPC768FD datasheet(37/64 Pages) PHILIPS

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Philips Semiconductors

Preliminary data

87LPC768

Low power, low price, low pin count (20 pin) microcontroller

with 4 kB OTP 8-bit A/D, Pulse Width Modulator

2001 Aug 06

Low Voltage EPROM Operation

The EPROM array contains some analog circuits that are not

required when VDD is less than 4 V, but are required for a VDD

greater than 4 V. The LPEP bit (AUXR.4), when set by software, will

power down these analog circuits resulting in a reduced supply

current. LPEP is cleared only by power-on reset, so it may be set

ONLY for applications that always operate with VDD less than 4 V.

Reset

The 87LPC768 has an active low reset input when configured for an

external reset. A fully internal reset may also be configured which

provides a reset when power is initially applied to the device. The

watchdog timer can act as an oscillator fail detect because it uses

an independent, fully on-chip oscillator.

The external reset input is disabled, and fully internal reset

generation enabled, by programming the RPD bit in the EPROM

configuration register UCFG1 to 0. EPROM configuration is

described in the section EPROM Characteristics

SU01391

87LPC768

VDD

8.2 k

RST

2.2

Figure 23. Typical External Reset Circuits

SU01170

CHIP RESET

CPU

CLOCK

RESET

TIMING

RPD (UCFG1.6)

WDT

MODULE

SOFTWARE RESET

SRST (AUXR1.3)

POWER MONITOR

RESET

RST/VPP PIN

WDTE (UCFG1.7)

Figure 24. Block Diagram Showing Reset Sources

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