ST7540 datasheet(38/44 Pages) STMICROELECTRONICS

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Auxiliary analog and digital functions

ST7540

38/44

7.7

Under voltage lock out

The UVLO function turns off the device if the VCC voltage falls under 4V. Hysteresis is

340mV typically.

7.8

Thermal shutdown

The ST7540 is provided of a thermal protection which turn off the PLI when the junction

temperature exceeds 170°C ±10% . Hysteresis is around 30°C.

When shutdown threshold is overcome, PLI interface is switched OFF.

Thermal Shutdown event is notified to the HOST controller using BU/THERM line. When

BU/THERM line is High, ST7540 junction temperature exceed the shutdown threshold (Not

Latched). This function is enabled only in Transmission mode (in Receiving mode the

BU/THERM pin is used for Band in Use signaling, see Band in Use function Section 7.1:

Band in use).

7.9

5V Voltage regulator

ST7540 has an embedded 5V linear regulator externally available (on pin VDC) to supply

the application circuitry. The 5V linear regulator has a very low quiescent current (50

µA) and

a current capability of 50mA. The regulator is protected against short circuitry events.

7.10

3.3V Voltage regulator

The VDD pin can act either as 3.3V Voltage Output or as Input Digital Supply. When the VDD

pin is externally forced to 5V all the Digital I/Os operate at 5V, otherwise all the Digital I/Os

are internally supplied at 3.3V. The VDD pin can also source 3.3V voltage to supply external

components. The 3.3V linear regulator has a very low quiescent current (50

µA) and a

current capability of 50mA. The regulator is protected against short circuitry events.

7.11

Power-up procedure

To ensure ST7540 proper power-Up sequence, VCC and VDD Supply has to fulfil the

following rules:

VCC rising slope must not exceed 100V/ms.

When VDD is below 5V/3.3V: VCC-VDD < 1.2V.

When VDD supply is connected to VDC (5V Digital Supply) the above mentioned relation

can be ignored if VDC load < 50mA and if the filtering capacitor on VDC < 100uF.

If VDD is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if VDD load <

50mA and the filtering capacitor on VDD < 100uF the second relation can be ignored .

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