Preliminary Technical Data

ADM1185

Rev. PrK | Page 5 of 12

PIN CONFIGURATIONS

1

2

3

4

ADM1185

TOP VIEW

(NOT TO SCALE)

Vcc

OUT2

OUT3

5

PWRGD

10

9

8

7

6

VIN4

VIN2

VIN1

VIN3

OUT1

GND

Figure 3. Pin Configurations

PIN FUNCTIONAL DESCRIPTIONS

Table 3.

Pin No.

Name

Description

1

GND

Chip Ground Pin.

2

VIN1

Non-inverting input of comparator 1. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

3

VIN2

Non-inverting input of comparator 2. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

4

VIN3

Non-inverting input of comparator 3. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

5

VIN4

Non-inverting input of comparator 4. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

6

PWRGD

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN4 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this

pin. After power-up (after PWRGD asserts) this output will be driven low if any of the voltages on the VIN1-

VIN4 pins falls below 0.6V.

7

OUT3

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN3 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low

if the voltage on VIN1 falls below 0.6V.

8

OUT2

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN2 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low

if the voltage on VIN1 falls below 0.6V.

9

OUT1

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN1 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this

pin. After power-up (after PWRGD asserts) this output will be driven low if the voltage on VIN1 falls below

0.6V.

10

VCC

Positive supply input pin. The operating supply voltage range is 2.7 V to 5.5 V.