6.3

Read status register (RDSR)

The read status register (RDSR) instruction is used to read the status register. The status register may be read at

any time, even while a write or write status register cycle is in progress. When one of these cycles is in progress,

it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is

also possible to read the Status register continuously, as shown in Figure 10.

Figure 10. Read Status register (RDSR) sequence

C

D

S

2

1

3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

0

MS47548V1

Q

Status Register Out

High impedance

MSB

MSB

7

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Status Register Out

The status and control bits of the status register are detailed in the following subsections.

6.3.1

WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write or write status register cycle.

When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress.

6.3.2

WEL bit

The WEL bit (write enable latch) bit is a flag that indicates the status of the internal write enable latch.

When WEL is set to 1, the internal write latch is set; when WEL is set to 0, the internal write enable latch is reset,

and no write or write status register instruction is accepted.

The WEL bit is returned to its reset state by the following events:

•

Power-up

•

Write disable (WRDI) instruction completion

•

Write status register (WRSR) instruction completion

•

Write (WRITE) instruction completion

6.3.3

BP1, BP0 bits

The block protect (BP1, BP0) bits are nonvolatile. They define the size of the area to be software-protected

against write instructions. These bits are written with the write status register (WRSR) instruction. When one

or both of the block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3. Write-

protected block size) becomes protected against write (WRITE) instructions. The block protect (BP1, BP0) bits

can be written provided that the hardware protected mode has not been set.

M95M02-DR M95M02-DF

Read status register (RDSR)

DS7024 - Rev 13

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