4.1

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two

modes:

•

CPOL = 0, CPHA = 0

•

CPOL = 1, CPHA = 1

For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available

from the falling edge of serial clock (C).

The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus master is in

stand-by mode and not transferring data:

•

C remains at 0 for (CPOL = 0, CPHA = 0)

•

C remains at 1 for (CPOL = 1, CPHA = 1)

Figure 6. SPI modes supported

MS42674V2

MSB

MSB

C

D

Q

C

CPOL

0

1

CPHA

0

1

M95M02-DR M95M02-DF

SPI modes

DS7024 - Rev 13

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