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HD74ACT112 데이터시트(PDF) 4 Page - Renesas Technology Corp

부품명 HD74ACT112
상세설명  Dual JK Negative Edge-Triggered Flip-Flop
PDF  10 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD74ACT112 데이터시트(HTML) 4 Page - Renesas Technology Corp

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HD74AC112/HD74ACT112
Rev.2.00, Jul.16.2004, page 2 of 7
Logic Symbol
3
J1
Q1
Q1
K1
CP1
CD1
J2
Q2
Q2
K2
CP2
CD2
SD1
SD2
5
410
11
13
12
6
9
7
1
2
15
14
VCC = Pin16
GND = Pin8
Pin Names
J
1, J2, K1, K2
Data Inputs
CP
1, CP2
Clock Pulse Inputs (Active Falling Edge)
C
D1, CD2
Direct Clear Inputs (Active Low)
S
D1, SD2
Direct Set Inputs (Active Low)
Q
1, Q2, Q1, Q 2
Outputs
Asynchronous Inputs:
Low input to
S
D sets Q to High level
Low input to
C
D sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on
C
D and SD makes both Q and Q High
Truth Table
Inputs
Outputs
@ t
n
@ t
n + 1
JK
Q
LL
Qn
LH
L
HL
H
HH
Qn
t
n
:
Bit time before clock pulse.
t
n + 1
:
Bit time after clock pulse.
H
:
High Voltage Level
L
:
Low Voltage Level



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