ICS844246DI Data Sheet

FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER

ICS844246DGI REVISION A NOVEMBER 28, 2012

6

©2012 Integrated Device Technology, Inc.

AC Electrical Characteristics

Table 6. LVDS AC Characteristics, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: See Phase Noise Plot.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

crosspoints.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

PLL_BYPASS = 0

50

333.33

MHz

In bypass mode with 25MHz Crystal,

PLL_BYPASS = 1 (default)

3.125

MHz

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 1

125MHz, Integration Range:

1.875MHz – 20MHz

0.416

0.560

ps

tsk(o)

Output Skew; NOTE 2, 3

45

ps

tR / tF

Output Rise/Fall Time

20% to 80%

220

380

ps

odc

Output Duty Cycle

45

55

%

tLOCK

PLL Lock Time

25

ms