전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

ICS8546-01 데이터시트(PDF) 2 Page - Renesas Technology Corp

부품명 ICS8546-01
상세설명  Low Skew, 1-to-6, Crystal-to-LVDS Fanout Buffer
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS8546-01 데이터시트(HTML) 2 Page - Renesas Technology Corp

  ICS8546-01 Datasheet HTML 1Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 2Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 3Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 4Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 5Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 6Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 7Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 8Page - Renesas Technology Corp ICS8546-01 Datasheet HTML 9Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 20 page
background image
ICS8546-01 Data Sheet
LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
2
©2011 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 2
nQ2, Q2
Output
Differential output pair. LVDS interface levels.
3, 22
VDDO
Power
Output supply pins.
4, 5
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
6
GND
Power
Power supply ground.
7, 8
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
9,
16
CLK_SEL0,
CLK_SEL1
Input
Pulldown
Clock select pins. LVCMOS/LVTTL interface levels.
10,
11
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
12
CLK_EN
Input
Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When
LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3.
13
CLK0
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
14
CLK1
Input
Pulldown
Non-inverting differential clock input.
15
nCLK1
Input
Pullup
Inverting differential clock input.
17, 18
nQ5, Q5
Output
Differential output pair. LVDS interface levels.
19
VDD
Power
Positive supply pin.
20, 21
nQ4, Q4
Output
Differential output pair. LVDS interface levels.
23, 24
nQ3, Q3
Output
Differential output pair. LVDS interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4pF
RPULLUP
Input Pullup Resistor
51
k
Ω
RPULLDOWN
Input Pulldown Resistor
51
k
Ω



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com