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ICS874208I 데이터시트(PDF) 14 Page - Renesas Technology Corp |
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ICS874208I 데이터시트(HTML) 14 Page - Renesas Technology Corp |
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14 / 20 page ![]() 874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 14 ©2014 Integrated Device Technology, Inc. Power Considerations This section provides information on power dissipation and junction temperature for the ICS874208I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874208I is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. • Power (core) MAX = V DD_MAX *(IDD_MAX + IDDO_MAX)= 2.625V * (15mA + 203mA) = 572.25mW • Power Dissipation for internal termination RT Power (RT)MAX = 4 * (VIN_MAX) 2 / RT_MIN = (1.2V)2 / 80 = 72mW Total Power_MAX = 572.25mW + 72mW = 644.25mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.644W * 33.1°C/W = 106.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA by Velocity Meters per Second 013 Multi-Layer PCB, JEDEC Standard Test Boards 33.1°C/W 28.1°C/W 25.4°C/W |
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