HMP8117 datasheet(21/45 Pages) RENESAS

21 / 45 page

HMP8117

FN4643 Rev 4.00

Page 21 of 45

July 29, 2009

In order to perform a read from a specific control register

within the HMP8117, an I2C bus write must first be

performed to properly setup the address register. Then an

I2C bus read can be performed to read from the desired

control register(s). As a result of needing the write cycle for a

read cycle there are actually two START conditions as

shown in Figure 19. The address register is then

auto-incremented after each byte read during the I2C read

cycle. Reserved registers return a value of 00H.

FIGURE 17. I2C TIMING DIAGRAM

SDA

SCL

tBUF

tLOW

tHIGH

tSU:DATA

tHD:DATA

tSU:STOP

SDA

SCL

START

CONDITION

1-7

ADDRESS

R/W

ACK

1-7

DATA

ACK

STOP

CONDITION

FIGURE 18. I2C SERIAL DATA FLOW

S = START CYCLE

P = STOP CYCLE

A = ACKNOWLEDGE

FROM MASTER

FROM HMP8117

0x88

DATA WRITE

DATA

0x88

DATA READ

NA = NO ACKNOWLEDGE

0x89

1000 1000 (R/W)

1000 1000

FIGURE 19. REGISTER WRITE/READ FLOW

CHIP ADDR

SUB ADDR

DATA

CHIP ADDR

SUB ADDR

CHIP ADDR

POINTED

TO BY

SUB ADDR

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

POINTED

TO BY

SUB ADDR

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

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