MPC93R51

REVISION 4 MARCH 14, 2016

3

©2013 Integrated Device Technology, Inc.

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

Table 1. Pin Description

Number

Name

Type

Description

PCLK, PCLK

Input

LVPECL

Differential clock reference

Low voltage positive ECL input

TCLK

Input

LVCMOS

Single ended reference clock signal or test clock

EXT_FB

Input

LVCMOS

Feedback signal input, connect to a QA, QB, QC, QD output

REF_SEL

Input

LVCMOS

Selects input reference clock

FSELA

Input

LVCMOS

Output A divider selection

FSELB

Input

LVCMOS

Output B divider selection

FSELC

Input

LVCMOS

Outputs C divider selection

FSELD

Input

LVCMOS

Outputs D divider selection

OE

Input

LVCMOS

Output enable/disable

QA

Output

LVCMOS

Bank A clock output

QB

Output

LVCMOS

Bank B clock output

QC0, QC1

Output

LVCMOS

Bank C clock outputs

QD0 – QD4

Output

LVCMOS

Bank D clock outputs

VCCA

Supply

VCC

Positive power supply for the PLL

VCC

Supply

VCC

Positive power supply for I/O and core

GND

Supply

Ground

Negative power supply

Table 2. Function Table

Control

Default

0

1

REF_SEL

0

Selects PCLK as reference clock

Selects TCLK as reference clock

PLL_EN

1

Test mode with PLL disabled. The input clock is

directly routed to the output dividers

PLL enabled. The VCO output is routed to the

output dividers

OE

0

Outputs enabled

Outputs disabled, PLL loop is open

VCO is forced to its minimum frequency

FSELA

0

QA = VCO

 2

QA = VCO

 4

FSELB

0

QB = VCO

 4

QB = VCO

 8

FSELC

0

QC = VCO

 4

QC = VCO

 8

FSELD

0

QD = VCO

 4

QD = VCO

 8

Table 3. Absolute Maximum Ratings(1)

Symbol

Characteristics

Min

Max

Unit

VCC

Supply Voltage

-0.3

4.6

V

VIN

DC Input Voltage

-0.3

VCC+0.3

V

VOUT

DC Output Voltage

-0.3

VCC+0.3

V

IIN

DC Input Current

20

mA

IOUT

DC Output Current

50

mA

TS

Storage Temperature

-55

150

°C