| 전자부품 데이터시트 검색엔진 |
|
MPC9448 데이터시트(PDF) 4 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
MPC9448 데이터시트(HTML) 4 Page - Renesas Technology Corp |
|
4 / 14 page ![]() MPC9448 Rev 7 3/15/16 4 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to +85°C) (1) 1. AC characteristics apply for parallel output termination of 50 to V TT. Symbol Characteristics Min Typ Max Unit Condition fref Input Frequency 0 350 MHz fMAX Maximum Output Frequency 0 350 MHz VPP Peak-to-Peak Input Voltage PCLK 400 1000 mV LVPECL VCMR (2) 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). Common Mode Range PCLK 1.3 VCC – 0.8 V LVPECL tP, REF Reference Input Pulse Width 1.4 ns tr, tf CCLK Input Rise/Fall Time 1.0(3) 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. ns 0.8 to 2.0 V tPLH/HL tPLH/HL Propagation Delay PCLK to any Q CCLK to any Q 1.6 1.3 3.6 3.3 ns ns tPLZ, HZ Output Disable Time 11 ns tPZL, LZ Output Enable Time 11 ns tS Setup Time CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 ns ns tH Hold Time CCLK to CLK_STOP PCLK to CLK_STOP 1.0 1.5 ns ns tsk(O) Output-to-Output Skew 150 ps tsk(PP) Device-to-Device Skew PCLK or CCLK to any Q 2.0 ns tSK(P) DCQ Output Pulse skew(4) Using CCLK Using PCLK Output Duty Cycle fQ<170 MHz 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |. 45 50 300 400 55 ps ps % DCREF = 50% tr, tf Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = -40°C to +85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input high voltage 1.7 VCC + 0.3 V LVCMOS VIL Input low voltage –0.3 0.7 V LVCMOS VPP Peak-to-peak input voltage PCLK 250 mV LVPECL VCMR (1) 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Common Mode Range PCLK 1.0 VCC – 0.7 V LVPECL IIN Input current(2) 2. Input pull-up / pull-down resistors influence input current. 300 A VIN = GND or VIN = VCC VOH Output High Voltage 1.8 V IOH = –15 mA (3) 3. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines at VCC = 2.5 V. VOL Output Low Voltage 0.6 V IOL= 15 mA (3) ZOUT Output impedance 19 ICCQ (4) 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Maximum Quiescent Supply Current 2.0 mA All VCC Pins |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |