MPC96877

548

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

Figure 1. MPC96877 Logic Diagram

Y1

Y1

Y0

Y0

Y3

Y3

Y2

Y2

Y5

Y5

Y4

Y4

Y7

Y7

Y6

Y6

Y9

Y9

Y8

Y8

FBOUT

FBOUT

LD*

PLL

LD* OR OE

LD*, OS or OE

PLL bypass

OE

OS

AVDD

CK

CK

10 K–100 K

Ω

GND

FBIN

FBIN

* The Logic Detect (LD) powers down the device when a

logic low is applied to both CK and CK.

Powerdown

Control and

Test Logic

MPC96877

1.8 V PLL 1:10 Differential SDRAM Clock Driver

NETCOM

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC96877

2