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ADF4002BCPZ 데이터시트(PDF) 19 Page - Analog Devices |
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ADF4002BCPZ 데이터시트(HTML) 19 Page - Analog Devices |
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19 / 24 page ![]() ADF4002 Rev. 0 | Page 19 of 24 The bottom of the lead frame chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. |
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