AND8020/D

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13

For the 10E series (ECL mode operation),

(

* 0.9) * (* 5.2)

Rt ) Rs ) Z0

y 0.531

Z0

*Z0 * Rs y Rt

7.10

(eq. 38)

For the 100E series (ECL mode operation),

(

* 0.955) * (* 4.5)

Rt ) Rs ) Z0

y 0.468

Z0

*Z0 * Rs y Rt

6.57

(eq. 39)

Parallel Fanout of Series Termination

An extension of the series termination technique, using

parallel fanout, eliminates the problem of lumped loading at

the expense of extra transmission lines (Figure 17).

Receiver

n

Figure 17. Parallel Fanout Using Series Termination

Receiver 1

Driver

N number of lines

Figure 17 shows a modification of the series termination

scheme in which several series terminated lines in parallel

fanout are driven using a single ECL gate. The principle

concern when applying this technique is to maintain the

current in the output emitter follower below the maximum

the circuit in terms of conductances.

Goutput u G1 ) G2 ) G

n

(eq. 40)

From Table B, for each of the series:

1

( Rt )

y

1

(

*Z01 * RS1)

)

1

(

*Z02 * RS2)

)

1

(

*Z0 * RS)

n

(eq. 41)

Where:

n = Number of Parallel Circuits

When:

Z01 + Z02 + Z0 , and RS1 + RS2 + RS

Rt x

(KZ0 *Z0 * Rs)

r

n

(eq. 43)

When a single series terminated line is driving more than

a single receiver, the maximum number of loads must be

addressed. The factor limiting the number of loads is the DC

voltage drop across the series termination resistor caused by

NMloss + IT *( Rs + RO )

(eq. 44)

Where:

Figure 18. Noise Margin Loss Example

Receiver 1

Driver

Receiver 2

Receiver

N

For the majority of ECL devices typical maximum value

for quiescent high state input current is 150 uA. Thus, for the

circuit shown in Figure 18, in which three gate loads are

present in a 50

W environment, the loss in high state noise

margin is calculated as:

NMloss + 3* * 150 mA * 50 W +* 22.5 mV

(eq. 45)

−22.5 mV.