X5643, X5645 (Replaces X25643, X25645)

FN8135 Rev 1.00

Page 2 of 19

July 18, 2005

PIN CONFIGURATION

8-Lead PDIP

CS/WDI

WP

SO

1

2

3

4

RESET/RESET

8

7

6

5

14-Lead SOIC

SO

WP

1

2

3

4

5

6

7

RESET/RESET

SCK

SI

14

13

12

11

10

9

8

NC

VCC

NC

X5643/45

SCK

SI

CS/WDI

NC

X5643/45

NC

VCC

VSS

CS/WDI

VCC

VSS

Pin

PDIP

Pin

SOIC

Pin TS-

SOP

Name

Function

1

2 & 3

2

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the de-

vice will be in the standby power mode. CS LOW enables the device, placing it

in the active power mode. Prior to the start of any operation after power-up, a

HIGH to LOW transition on CS is required.

Watchdog Input.

A HIGH to LOW transition on the WDI pin restarts the watchdog

timer. The absence of a HIGH to LOW transition within the watchdog time out

period results in RESET/RESET going active.

24

3

SO

Serial Output.

SO is a push/pull serial data output pin. A read cycle shifts data out

on this pin. The falling edge of the serial clock (SCK) clocks the data out.

59

13

SI

Serial Input.

SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin. The rising edge of the serial clock (SCK) latches the input

data. Send all opcodes (Table 1), addresses and data MSB first.

610

14

SCK

Serial Clock.

The serial clock controls the serial bus timing for data input and out-

put. The rising edge of SCK latches in the opcode, address, or data bits present on

the SI pin. The falling edge of SCK changes the data output on the SO pin.

35

7

WP

Write Protect.

The WP pin works in conjunction with a nonvolatile WPEN bit to

“lock” the setting of the watchdog timer control and the memory write protect bits.

46

8

VSS

Ground

8

12 & 13

19

VCC

Supply Voltage

7

11

18

RESET/

RESET

Reset Output

. RESET/RESET is an active LOW/HIGH, open drain output

which goes active whenever VCC falls below the minimum VCC sense level. It

will remain active until VCC rises above the minimum VCC sense level for

200ms. RESET/RESET goes active if the watchdog timer is enabled and CS

remains either HIGH or LOW longer than the selectable watchdog time out pe-

riod. A falling edge of CS will reset the watchdog timer. RESET/RESET goes

active on power-up at about 1V and remains active for 200ms after the power

supply stabilizes.

1, 7, 8,

14

1, 4-6,

9-12,

15-17, 20

NC

No internal connections