LT1725CS datasheet(21/28 Pages) LINER

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LT1725

1725f

SWITCH NODE CONSIDERATIONS

For maximum efficiency, gate drive rise and fall times are

made as short as practical. To prevent radiation and high

frequency resonance problems, proper layout of the

components connected to the IC is essential, especially

the power paths (primary and secondary). B field (mag-

netic) radiation is minimized by keeping MOSFET leads,

output diode, and output bypass capacitor leads as short

as possible. E field radiation is kept low by minimizing the

length and area of all similar traces. A ground plane

should always be used under the switcher circuitry to

prevent interplane coupling.

The high speed switching current paths are shown sche-

matically in Figure 8. Minimum lead length in these paths

are essential to ensure clean switching and minimal EMI.

The path containing the input capacitor, transformer pri-

mary and MOSFET, and the path containing the trans-

former secondary, output diode and output capacitor

contain “nanosecond” rise and fall times. Keep these

paths as short as possible.

APPLICATIO S I FOR ATIO

GATE DRIVE RESISTOR CONSIDERATIONS

The gate drive circuitry internal to the LT1725 has been

designed to have as low an output impedance as practi-

cally possible—only a few ohms. A strong L/C resonance

is potentially presented by the inductance of the path

leading to the gate of the power MOSFET and its overall

gate capacitance. For this reason the path from the GATE

package pin to the physical MOSFET gate should be kept

as short as possible, and good layout/ground plane prac-

tice used to minimize the parasitic inductance.

An explicit series gate drive resistor may be useful in some

applications to damp out this potential L/C resonance

(typically tens of MHz). A minimum value of perhaps

several ohms is suggested, and higher values (typically a

few tens of ohms) will offer increased damping. However,

as this resistor value becomes too large, gate voltage rise

time will increase to unacceptable levels, and efficiency

will suffer due to the sluggish switching action.

Figure 8. High Speed Current Switching Paths

PGND

GATE

1725 F08

GATE

DISCHARGE

PATH

PRIMARY

POWER

PATH

SECONDARY

POWER

PATH

VCC

VIN

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