HC705C9AGRSSLASHD datasheet(107/157 Pages) NXP

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General Release Specification

SPI Registers

MC68HC705C9A — Rev. 2.0

Serial Peripheral Interface

10.6.2 Serial Peripheral Status Register (SPSR)

The SPI status register, shown in Figure 10-5, contains flags to signal

the following conditions:

•

SPI transmission complete

•

Write collision

•

Mode fault

SPIF — SPI Transfer Complete Flag

The serial peripheral data transfer flag bit is set upon completion of

data transfer between the processor and external device. If SPIF

goes high, and if SPIE is set, a serial peripheral interrupt is generated.

Clearing the SPIF bit is accomplished by reading the SPSR (with

SPIF set) followed by an access of the SPDR. Following the initial

transfer, unless SPSR is read (with SPIF set) first, attempts to write to

SPDR are inhibited.

Table 10-1. SPI Clock

Rate Selection

SPR[1:0]

SPI Clock Rate

Internal Clock

÷ 2

Internal Clock

÷ 4

Internal Clock

÷ 16

Internal Clock

÷ 32

SPSR

Bit 7

654321

Bit 0

Read:

SPIF

WCOL

MODF

0000

Write:

Reset:

00000000

= Unimplemented

Figure 10-5. SPI Status Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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