ISL70005SEH, ISL73005SEH

3. Typical Performance Curves

R34DS0008EU0103 Rev.1.03

Page 21 of 45

Jul 28, 2022

Figure 42. LDO Constant Current Limit Threshold

Figure 43. LDO Load Regulation DDR3 Configuration

Figure 44. LDO Load Regulation DDR2 Configuration

Figure 45. LDO Load Regulation DDR Configuration

Figure 46. LDO Load Regulation Av = 2

Figure 47. LDO Load Regulation Av = 3

Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;

fSW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF

tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

LDO Current (A)

0.740

0.745

0.750

0.755

0.760

0.765

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

LDO Current (A)

L_VCC = B_VCC = 5V

L_VIN = 1.5V

L_EA+ = 0.75V

0.890

0.895

0.900

0.905

0.910

0.915

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

LDO Current (A)

L_VCC = B_VCC = 5V

L_VIN = 1.8V

L_EA+ = 0.9V

1.240

1.245

1.250

1.255

1.260

1.265

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

LDO Current (A)

L_VCC = B_VCC = 5V

L_VIN = 2.5V

L_EA+ = 1.25V

1.18

1.19

1.20

1.21

1.22

1.23

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Load Current (A)

L_VIN = 3V

L_VCC = B_VCC = 5V

L_EA+ = VREF

1% Resistor Divider

1.78

1.79

1.80

1.81

1.82

1.83

1.84

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Load Current (A)

L_VIN = 3V

L_VCC = B_VCC = 5V

L_EA+ = VREF

1% Resistor Divider