DLPA2000 datasheet(13/68 Pages) TI

13 / 68 page

6.5 Power Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER(3) (4) (5)

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

I(VDD) +

I(VDD_PLLM) +

I(VDD_PLLD)

1.1-V rails

Frame rate = 50 Hz

Input = 1920 x 1080 to FPGA

210

327

Frame rate = 60 Hz

Input = 1920 x 1080 to FPGA

194

354

I(VDD_PLLM)

MCG PLL 1.1-V current(6)

Frame rate = 50 Hz

Input = 1920 x 1080 to FPGA

Frame rate = 60 Hz

Input = 1920 x 1080 to FPGA

I(VDD_PLLD)

DCG PLL 1.1-V current(6)

Frame rate = 50 Hz

Input = 1920 x 1080 to FPGA

Frame rate = 60 Hz

Input = 1920 x 1080 to FPGA

I(VCC18)

All 1.8-V I/O current: (1.8-V power supply

for all I/O other than the host or parallel

interface and the SPI flash interface)

Frame rate = 50 Hz

Input = 1920 x 1080 to FPGA

Frame rate = 60 Hz

Input = 1920 x 1080 to FPGA

I(VCC_INTF)

Host or parallel interface I/O current: 1.8

V (includes IIC0, PDATA, video syncs, and

HOST_IRQ pins)(6)

Frame rate = 50 Hz

Input = 1920 x 1080 to FPGA

Frame rate = 60 Hz

Input = 1920 x 1080 to FPGA

I(VCC_FLSH)

Flash interface I/O current: 1.8 to 3.3 V(6)

Frame rate = 50 Hz

Input = 1920 x 1080 to FPGA

Frame rate = 60 Hz

Input = 1920 x 1080 to FPGA

(1)

Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.

(2)

Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.

(3)

Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum

nominal voltage (that is 1.8 V).

(4)

Input image is 1920 × 1080 (1080p) 24 bits using reduced VESA timings on the parallel interface at the frame rate shown with the

0.23-in 1080p (DLP230NP/NPSE ) DMD. The controller has the CAIC and LABB algorithms turned off.

(5)

The values do not take into account software updates or customer changes that may affect power performance.

(6)

This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor,

30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells.

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DLPC3436

DLPS156E – JANUARY 2019 – REVISED APRIL 2023

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