APR12SLASHD datasheet(88/101 Pages) NXP

88 / 101 page

4-14

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

Application Examples

Figure 4-5

shows a circuit that waits until VCC on the DSP56001A is at least 4.5 V before initiating

a 75,000

× T

C oscillator stabilization delay required for the on-chip oscillator (only 25 × TC is

required for an external oscillator). This insures that the DSP is operational and stable before

releasing the reset signal.

Figure 4-5 Reset Circuit Using MC34064/MC33064

Note:

IRQA, and IRQB must be driven to the logic levels appropriate for the application.

MODA and MODB must be driven to the logic levels appropriate for the application.

RESET

1.2 VREF

+5V

MC34064

MC33064

2 (2)

3 (4)

1 (1)

CDLY

tDLY = RCDLY In

1 -

VTH

VIN - VOL

Where:

Logic

Reset

tDLY = 75,000 TC minimum

VIN = 5 V

fOSC = 20 MHz

VTH = 2.5 V

VOL = 0.4 V

CDLY = 1 mf ± 20%

TC = 50 ns

R = 8.2 K

± 5%

–

AA0908

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

APR12/D 데이터시트(PDF) 88 Page - NXP Semiconductors

APR12/D 데이터시트(HTML) 88 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL