전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD9411/PCB 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD9411/PCB
상세설명  10-Bit, 170/200 MSPS 3.3 V A/D Converter
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9411/PCB 데이터시트(HTML) 6 Page - Analog Devices

Back Button AD9411/PCB Datasheet HTML 2Page - Analog Devices AD9411/PCB Datasheet HTML 3Page - Analog Devices AD9411/PCB Datasheet HTML 4Page - Analog Devices AD9411/PCB Datasheet HTML 5Page - Analog Devices AD9411/PCB Datasheet HTML 6Page - Analog Devices AD9411/PCB Datasheet HTML 7Page - Analog Devices AD9411/PCB Datasheet HTML 8Page - Analog Devices AD9411/PCB Datasheet HTML 9Page - Analog Devices AD9411/PCB Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 28 page
background image
AD9411
Rev. A | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
AD9411-170
AD9411-200
Parameter (Conditions)
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
Maximum Conversion Rate1
Full
VI
170
200
MSPS
Minimum Conversion Rate
1
Full
V
40
40
MSPS
CLK+ Pulse Width High (tEH)
1
Full
IV
2
12.5
2
12.5
ns
CLK+ Pulse Width Low (tEL)
1
Full
IV
2
12.5
2
12.5
ns
OUTPUT (LVDS Mode)
Valid Time (tV)
Full
VI
2.0
2.0
ns
Propagation Delay (tPD)
Full
VI
3.2
4.3
3.2
4.3
ns
Rise Time (tR) (20% to 80%)
25°C
V
0.5
0.5
ns
Fall Time (tF) (20% to 80%)
25°C
V
0.5
0.5
ns
DCO Propagation Delay (tCPD)
Full
VI
1.8
2.7
3.8
1.8
2.7
3.8
ns
Data to DCO Skew (tPD–tCPD)
Full
IV
0.2
0.5
0.8
0.2
0.5
0.8
ns
Latency
Full
IV
14
14
Cycles
Aperture Delay (tA)
25°C
V
1.2
1.2
ns
Aperture Uncertainty (Jitter, tJ)
25°C
V
0.25
0.25
ps
rms
Out-of-Range Recovery Time
25°C
V
1
1
Cycles
1 All ac specifications tested by driving CLK+ and CLK– differentially.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI.
100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
CLK+
AIN
tEH
tEL
tPD
tCPD
1/fS
DCO+
DCO–
N–1
N–14
N–13
N
14 CYCLES
N+1
N+1
N
CLK–
DATA OUT
Figure 2. LVDS Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com