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AD9511-VCO/PCB 데이터시트(PDF) 46 Page - Analog Devices

부품명 AD9511-VCO/PCB
상세설명  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
PDF  60 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9511-VCO/PCB 데이터시트(HTML) 46 Page - Analog Devices

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AD9511
Rev. A | Page 46 of 60
Addr
(Hex)
Parameter
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Def.
Value
(Hex)
Notes
OUTPUTS
3D
LVPECL OUT0
Not Used
Output Level
<3:2>
Power-Down <1:0>
08
ON
3E
LVPECL OUT1
Not Used
Output Level
<3:2>
Power-Down <1:0>
08
ON
3F
LVPECL OUT2
Not Used
Output Level
<3:2>
Power-Down <1:0>
08
ON
40
LVDS_CMOS
OUT 3
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02
LVDS, ON
41
LVDS_CMOS
OUT 4
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02
LVDS, ON
42,
43,
44
Not Used
CLK1 AND
CLK2
Input
Receivers
45
Clocks Select,
Power-Down
(PD) Options
Not Used
CLKs in
PD
REFIN PD
CLK
to
PLL
PD
CLK2
PD
CLK1
PD
Select
CLK IN
01
All Clocks
ON, Select
CLK1
46,
47,
48, 49
Not Used
DIVIDERS
4A
Divider 0
Low Cycles <7:4>
High Cycles <3:0>
00
Divide by 2
4B
Divider 0
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
4C
Divider 1
Low Cycles <7:4>
High Cycles <3:0>
11
Divide by 4
4D
Divider 1
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
4E
Divider 2
Low Cycles <7:4>
High Cycles <3:0>
33
Divide by 8
4F
Divider 2
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
50
Divider 3
Low Cycles <7:4>
High Cycles <3:0>
00
Divide by 2
51
Divider 3
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
52
Divider 4
Low Cycles <7:4>
High Cycles <3:0>
11
Divide by 4
53
Divider 4
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
54,
55,
56,
57
Not Used
FUNCTION
58
FUNCTION
Pin and Sync
Not
Used
Set FUNCTION Pin
PD Sync
PD All
Ref
Sync
Reg
Sync
Select
Sync
Enable
00
FUNCTION
Pin =
RESETB
59
Not Used
5A
Update
Registers
Not Used
Update
Registers
00
Self-
Clearing
Bit
END



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