LT3756 datasheet(23/31 Pages) AD

23 / 31 page

LT8355-1

Rev. A

For more information www.analog.com

Figure 8. Dual Boost Reference Layout for LT8355-1

9 10 11 12 13

28 27 26 25 24

FB1

ISP1

PWMTG1

GND

FB2

ISP2

ISN2

PWMTG2

INTVCC

LED+2

SENSEP2

SENSEP1

VIN

ISN1

GND

LED+1

GND

SW1

SW2

GATE1

GATE2

GND

VIN

GND

VIA

ROUTING ON THE 2ND PLANE

8355-1 F08

APPLICATIONS INFORMATION

performance. Keep the output capacitor and catch diode

as close as possible to the external NMOS switch and

switch current sense resistor to help this. For more infor-

mation about hot loops see Analog Devices Application

Notes AN136 and AN139.

An example 2-layer layout which takes the above consid-

erations into account is provided in Figure 8. It is imper-

ative that the layout of any PCB carefully consider the

capabilities of the PCB manufacturer and other applica-

tion constraints. The example provided here should guide

the layout of an application PCB. If the application or

manufacturing capabilities mandate a different layout, be

sure to keep the above guidance in mind for all changes.

Note that the 4-layer layout is recommended for best per-

formance. Please refer to the EVAL-LT8355-1-AZ eval-

uation circuit for a 4-layer PCB reference layout design.

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