PID9v-604e Hardware Specifications

13

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Rise time (all signals except

ARTRY, SHD, ABB, DBB, TS,

and XATS)

1.0

1.0

1.0

1.0

ns

6

Fall time (ARTRY, SHD, ABB,

DBB, TS, and XATS)

1.0

1.0

1.0

1.0

ns

6

Fall time (all signals except

ARTRY, SHD, ABB, DBB, TS,

and XATS)

1.0

1.0

1.0

1.0

ns

6

Notes:

1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or

2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4).

2. This minimum parameter assumes CL = 0 pF.

3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external

voltage from 5.5 V to 0.8 V instead of from 3.6 V to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).

4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk

the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time

duration (in nanoseconds) of the parameter in question.

5. Fast Out mode (L2_TSTCLK = GND) improves output valid timing and reduces output hold times. The 604e

powers up in Compatibility mode in a 604 system (L2_TSTCLK = OVdd).

6. These specifications are nominal values.

7. These timing specifications are tested with drive mode signals configured with DRVMODE0 = low,

DRVMODE1 = high.

Table 8. Output AC Timing Specifications1 (Continued)

Vdd = AVdd = 2.5

± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C, Drive mode [01]7

Num

Characteristic

166.67 MHz

180, 200, 225, and 233 MHz

Unit Notes

Min

Max

Fast Out

Min/Max

Min

Max

Fast Out

Min/Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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