MPC604ECSLASHD datasheet(6/32 Pages) NXP

6 / 32 page

604 Hardware Specifications

Preliminary/Subject to Change without Notice

Figure 3 provides the timing diagram for the fast-L2 mode select input.

Figure 3. Fast-L2 Mode Select Input Timing Diagram

1.3.3 Output AC Speciﬁcations

Table 7 provides the output AC timing speciﬁcations for the 604 (shown in Figure 4).

Table 7. PowerPC 604 Microprocessor Output AC Timing Specifications

Vdd = 3.3

± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ Tj ≤ 105 °C

Num

Characteristic

100 MHz

120 MHz

133 MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

SYSCLK to output driven

(output enable time)

0.75

—

0.75

—

0.75

—

13a

SYSCLK to TS, XATS, ARTRY, SHD,

ABB, and DBB output valid (for 5.5 V to

0.8 V)

—

8.5

—

7.5

—

7.0

13b

SYSCLK to TS, XATS, ARTRY, SHD,

ABB, and DBB output valid (for 3.6 V to

0.8 V)

—

7.5

—

6.5

—

6.0

14a

SYSCLK to all other signals output valid

(for 5.5 V to 0.8 V)

—

8.5

—

7.5

—

7.0

14b

SYSCLK to all other signals output valid

(for 3.6 V to 0.8 V)

—

7.5

—

6.5

—

6.0

SYSCLK to output invalid (output hold)

1.0

—

1.0

—

1.0

—

SYSCLK to output high impedance (all

signals except ARTRY, SHD, ABB, DBB,

TS, and XATS)

—

7.0

—

6.5

—

6.0

SYSCLK to output high impedance TS,

XATS

—

7.0

—

6.5

—

6.0

SYSCLK to ABB and DBB high

impedance after precharge

—

1.0*

tsysclk

—

1.0*

tsysclk

—

1.0*

tsysclk

SYSCLK to ARTRY and SHD high

impedance before precharge

—

7.0

—

6.5

—

6.0

FAST-L2 MODE PIN

HRESET

VM = Midpoint Voltage (1.4V)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

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