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ADAV400 데이터시트(PDF) 27 Page - Analog Devices |
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ADAV400 데이터시트(HTML) 27 Page - Analog Devices |
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27 / 36 page ![]() ADAV400 Rev. 0 | Page 27 of 36 LRCLK BCLK SDATA MSB LEFT CHANNEL LSB MSB RIGHT CHANNEL LSB 1 /FS Figure 31. I2S Mode—16 to 24 Bits per Channel LRCLK BCLK SDATA LEFT CHANNEL MSB LSB MSB RIGHT CHANNEL LSB 1 /FS Figure 32. Left-Justified Mode—16 to 24 Bits per Channel LRCLK BCLK SDATA LEFT CHANNEL MSB LSB MSB RIGHT CHANNEL LSB 1 /FS Figure 33. Right-Justified Mode—16 to 24 Bits per Channel LRCLK BCLK DATA SLOT 0 SLOT 1 SLOT 4 SLOT 5 32 BCLKs MSB MSB–1 MSB–2 256 BCLKs SLOT 2 SLOT 3 SLOT 6 SLOT 7 LRCLK BCLK DATA Figure 34. 8-Channel TDM Mode with Clock LRCLK CH 0 BCLK SDATA MSB TDM 8TH CH 32 BCLKs MSB TDM SLOT 0 SDIN0L SLOT 1 SDIN0R SLOT 4 SDIN2L SLOT 5 SDIN2R SLOT 2 SDIN1L SLOT 3 SDIN1R SLOT 6 SDIN3L SLOT 7 SDIN3R Figure 35. TDM Mode with Pulse Word Clock |
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