VPA2000 datasheet(21/25 Pages) RENESAS

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VPA2000

Product Data

March 11, 2010

LAYOUT GUIDELINES

To optimize the device performance, follow these layout

guidelines:

Place the inductor and diode as close as possible to

Pin19 (SWN).

Pin20 (GND1) is the power ground of the boost

converter. Return the boost output capacitors’ ground

connections to this pin while minimizing the loop area

created from pin 19 through the diode D1, through the

output capacitors, and back to pin 20.

Separate all grounds on the top layer and connect all

ground connections through vias to the ground plane.

Locate all feedback resistor dividers close to the

feedback pins. Keep the traces from feedback pins to

the resistor dividers as short as possible.

Keep the traces from SWN to CGHFLY to D2 and D3

short.

Keep the traces from SWN to CGLFLY to D4 and D5

short.

Place output capacitors COUT1, CLDO, and CVCORE close

to their respective output pins.

Keep all input decoupling capacitors close to the input

pins and return their ground connections directly to

the appropriate ground pin.

Copper

AVDD

VIN

Vias to

ground

plane

Vias to

power

plane

Vias to

ground

plane

CAVDD1

CAVDD2

Figure 38. Optimized Layout for Boost Converter

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