CS5320 datasheet(74/160 Pages) AMCC

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S5320 – PCI Match Maker: Operation Registers

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Table 35. Interrupt Control Status Register

Bit

Description

31:24

Reserved. Always zero.

Interrupt Asserted. This read-only status bit indicates that one or more interrupt conditions are present. This bit

is the OR of the interrupt sources described by bits 20, 17 and 16 of this register.

22:21

Reserved. Always zero.

BIST. Built-In Self-Test Interrupt. This interrupt occurs when a self test is initiated by the PCI interface by writing

to the PCI configuration register BIST. This bit will stay set until cleared by writing a 1 to this location. Self test

completion codes may be passed to the PCI BIST register by writing to the ARCR register.

19:18

Reserved. Always zero.

Outgoing Mailbox Interrupt. This bit can be set when the mailbox is read by the PCI interface. This bit operates

as read or write 1 clear. A write with the data as 1 will cause this bit to be reset; a write with the data as 0 will not

change the state of this bit.

Incoming Mailbox Interrupt. This bit can be set when the mailbox is written by the PCI interface. This bit oper-

ates as read or write 1 clear. A write with the data as 1 will cause this bit to be reset; a write with the data as 0

will not change the state of this bit.

15:13

Reserved. Always zero.

Enable Outgoing Mailbox Interrupt. This bit allows a PCI read of the outgoing mailbox register to produce an

Add-On interrupt. This bit is read/write.

11:10

Hardwired to 11.

9:8

Outgoing Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt.

[00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write.

7:5

Reserved. Always zero.

Enable Incoming Mailbox Interrupt. This bit allows a write from the PCI bus to the incoming mailbox register to

produce an Add-On interrupt. This bit is read/write.

3:2

Hardwired to 1.

1:0

Incoming Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt. 00b

selects byte 0, 01b selects byte 2, and 11b selects byte 3. This field is read/write.

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