CS5920 datasheet(147/160 Pages) AMCC

147 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

147

Data Book

TIMING SPECIFICATION

PCI Clock Specification

Table 5 summarizes the A. C. characteristics for the PCI bus signals as they apply to the S5920. The figures after

Table 5 visually indicate the timing relationships.

Notes:

1. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion

of the clock waveform as shown in Figure 1.

2. Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load.

3. For purposes of Active/Float timing measurements, the Hi-Z or 'off" state is defined to be when the total current delivered through the compo-

nent pin is less than or equal to the leakage current specification.

4. See the timing measurement conditions in Figure 3.

Figure 83. PCI Clock Timing

Table 63. Functional Operation Range

(VCC = 5.0V +/- 5%, 0O C to 70 OC, 50 pF load on outputs for MAX, 0 pF load for MIN)

Symbol

Parameter

Min

Max

Units

Notes

Tcyc

Clock Time

CLK High Time

CLK Low Time

Rise Time (0.8V to 2.0V)

V/ns

Fall Time (2.0V to 0.8V)

V/ns

CLK to Signal Valid Delay (Bused Signals)

CLK to Signal Valid Delay (Point-to-Point Signals)

1,2

Float to Active Delay

Active to Float Delay

Rising Edge Setup

Hold from PCI Clock Rising Edge

2.0

0.8

2.0

0.8

2.0

0.8

TCL

IH2

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