CS5920 datasheet(41/160 Pages) AMCC

41 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

PCI STATUS REGISTER (PCISTS)

This register contains PCI device status information.

This register is defined by the PCI specification and its

implementation is required of all PCI devices. Only

applicable bits are used by the S5920; those which are

not used are hardwired to 0. Status bits within this reg-

ister are designated as “write one clear,” meaning that

in order to clear a given bit, a 1 must be written. All R/

W/C bits written with a 0 are left unchanged. These

bits are identified in Figure 4 as (R/WC). Those which

are Read Only are shown as (RO).

Figure 10. PCI Status Register

PCI Status

Address Offset:

06h-07h

Power-up value:

0200h

Boot-load:

not used

Attribute:

Read Only Read/Write Clear

Size:

16 bits

Reserved = 00's

Reserved (RO)

Fast Back-to-Back Capable

(RO)

Data Parity Reported (RO)

DEVSEL# Timing Status

00 = Fast

01 = Medium

10 = Slow

11 = Reserved

Signaled Target Abort (R/WC)

Received Target Abort (RO)

Received Master Abort (RO)

Signaled System Error (R/WC)

Detected Parity Error (R/WC)

66 Mhz Capable

UDF Supported

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