LPC86X datasheet(2/99 Pages) NXP

2 / 99 page

LPC86x

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Product data sheet

Rev.3 — 28 April 2023

2 of 97

NXP Semiconductors

LPC86x

32-bit Arm Cortex-M0+ microcontroller



High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and digital filter. GPIO direction

control supports independent set/clear/toggle of individual bits. The GPIO pins are

tri-state when power is on.



High-current source output driver (20 mA) on four pins.



High-current sink driver (20 mA) on two true open-drain pins.



GPIO interrupt generation capability with a boolean pattern-matching feature on

eight GPIO inputs.



Switch matrix for flexible configuration of each I/O pin function.



CRC engine.



DMA with 16 channels and 13 trigger inputs.



Timers:



Two FlexTimers with DMA support and a selection of hardware triggers. The first

FlexTimer has six channels and includes support for motor control (including Fault

Control). The second FlexTimer has four channels. This timer does not include

Fault Control but includes a Quadrature Decoder interface. Both FlexTimers are

clocked up to 60 MHz.



Four-channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.



Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a

low-power, low-frequency internal oscillator, or an external clock input in the

always-on power domain.



Windowed Watchdog timer (WWDT).



Analog peripherals:



One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.9 Msamples/s. The ADC supports

two independent conversion sequences.



Comparator with five input pins and external or internal reference voltage.



Serial peripherals:



Three USART interfaces with pin functions are assigned through the switch matrix,

support receives idle interrupt, and two fractional baud rate generators.



Two SPI controllers with pin functions are assigned through the switch matrix.



One I2C-bus interface. I2C supports Fast-mode Plus with a 1 Mbit/s data rate on

two true open-drain pins and listen mode.



One controller/target I3C-MIPI bus interface. The I3C supports DDR. It is supported

by the general-purpose DMA controller.



Clock generation:



Free Running Oscillator (FRO). This oscillator provides selectable 60 MHz, 48

MHz, and 36 MHz outputs that can be used as a system clock. Also, these outputs

can be divided down to 30 MHz, 24 MHz, and 18 MHz for the system clock. The

FRO is trimmed to

1 % accuracy over the entire voltage and temperature range of

0 °C to 70 °C.



External clock input for clock frequencies of up to 25 MHz.



Crystal oscillator with an operating range of 1 MHz to 25 MHz.



1 MHz (+3%) low-power oscillator (LPOSC) can be used as a clock source for the

watchdog timer.

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