1112F—02/27/09

ICS9LP505-1

64-pin CK505 for Desktop Systems

IDT® 64-pin CK505 for Desktop Systems

9

AC Electrical Characteristics - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

NOTES

Rising Edge Slew Rate

t

SLR

Averaging on

2.5

8

V/ns

2, 3

Falling Edge Slew Rate

t

FLR

Averaging on

2.5

8

V/ns

2, 3

Slew Rate Variation

t

SLVAR

Averaging on

20

%

1, 10

Differential Voltage Swing

V

SWING

Averaging off

300

mV

2

Crossing Point Voltage

V

XABS

Averaging off

300

550

mV

1,4,5

Crossing Point Variation

V

XABSVAR

Averaging off

140

mV

1,4,9

Maximum Output Voltage

V

HIGH

Averaging off

1150

mV

1,7

Minimum Output Voltage

V

LOW

Averaging off

-300

mV

1,8

Duty Cycle

D

CYC

Averaging on

45

55

%

2

CPU Skew

CPU

SKEW

Averaging on

100

ps

SRC Skew

SRC

SKEW

Averaging on

3000

ps

6

1Measurement taken for single ended waveform on a component test board (not in system)

2 Measurement taken from differential waveform on a component test board. (not in system)

3 Slew rate emastured through V_swing voltage range centered about differential zero

4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)

9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting

C_cross_delta to be smaller than V_Cross absolute.

5 Only applies to the differential rising edge (Clock rising, Clock# falling)

NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.

7 The max voltage including overshoot.

8 The min voltage including undershoot.

10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The

median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.

Clock Jitter Specs - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

NOTES

CPU Jitter - Cycle to Cycle

CPUJ

C2C

Differential Measurement

85

ps

1

SRC Jitter - Cycle to Cycle

SRCJ

C2C

Differential Measurement

125

ps

1,2

DOT Jitter - Cycle to Cycle

DOTJ

C2C

Differential Measurement

250

ps

1

NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

1JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded.

The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured ina real system.

2 Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a componnet test board under quiet

condittions with all outputs on. Jitter analysis is performed using the standardized tool provided by the PCI SIG.