AD9397SLASHPCB datasheet(12/28 Pages) AD

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AD9397

Rev. 0 | Page 12 of 28

4:4:4 TO 4:2:2 FILTER

The AD9397 contains a filter that allows it to convert a signal

from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the

maximum accuracy and fidelity of the original signal.

Input Color Space to Output Color Space

The AD9397 can support a wide variety of output formats,

such as:

•

RGB 24-bit

•

4:4:4 YCrCb 8-bit

•

4:2:2 YCrCb 8-bit, 10-bit, and 12-bit

•

Dual 4:2:2 YCrCb 8-bit

Color Space Conversion (CSC) Matrix

The CSC matrix in the AD9397 consists of three identical

processing channels. In each channel, three input values are

multiplied by three separate coefficients. Also included are an

offset value for each row of the matrix and a scaling multiple

for all values. Each value has a 13-bit, twos complement

resolution to ensure the signal integrity is maintained. The

CSC is designed to run at speeds up to 150 MHz supporting

resolutions up to 1080p at 60 Hz. With any-to-any color space

support, formats such as RGB, YUV, YCbCr, and others are

supported by the CSC.

The main inputs, RIN, GIN, and BIN, come from the 8-bit to 12-bit

inputs from each channel. These inputs are based on the input

format detailed in Table 9. The mapping of these inputs to the

CSC inputs is shown in Table 8.

Table 8. CSC Port Mapping

Input Channel

CSC Input Channel

R/CR

RIN

Gr/Y

GIN

B/CB

One of the three channels is represented in Figure 6. In each

processing channel, the three inputs are multiplied by three

separate coefficients marked a1, a2, and a3. These coefficients

are divided by 4096 to obtain nominal values ranging from

–0.9998 to +0.9998. The variable labeled a4 is used as an offset

control. The CSC_Mode setting is the same for all three

processing channels. This multiplies all coefficients and offsets

by a factor of 2CSC_Mode.

The functional diagram for a single channel of the CSC, as

shown in Figure 6, is repeated for the remaining G and B

channels. The coefficients for these channels are b1, b2, b3, b4,

c1, c2, c3, and c4.

×2

a1[12:0]

a2[12:0]

a3[12:0]

RIN [11:0]

GIN [11:0]

BIN [11:0]

×4

CSC_Mode[1:0]

a4[12:0]

ROUT [11:0]

4096

Figure 6. Single CSC Channel

A programming example and register settings for several

common conversions are listed in the Color Space Converter

(CSC) Common Settings section.

For a detailed functional description and more programming

examples, refer to the Application Note AN-795, AD9880 Color

Space Converter User's Guide.

OUTPUT DATA FORMATS

The AD9398 supports 4:4:4, 4:2:2, double data-rate (DDR), and

BT656 output formats. Register 0x25[3:0] controls the output

mode. These modes and the pin mapping are illustrated in

Table 8.

Table 9.

Port

Red

Green

Blue

Bit

4:4:4

Red/Cr [7:0]

Green/Y [7:0]

Blue/Cb [7:0]

4:2:2

CbCr [7:0]

Y [7:0]

DDR 4:2:2 ↑ CbCr ↓ Y, Y

DDR ↑ 1 G [3:0]

DDR ↑ B [7:4]

DDR ↑ B [3:0]

DDR 4:2:2 ↑ CbCr [11:0]

4:4:4 DDR

DDR ↓ R [7:0]

DDR ↓ G [7:4]

DDR 4:2:2 ↓ Y,Y [11:0]

4:2:2 to 12

CbCr[11:0]

Y [11:0]

1 Arrows in the table indicate clock edge. Rising edge of clock =

↑, falling edge = ↓.

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